TLB and SOCAMM: The Nvidia Capacity Cut That Misses the Substrate Maker

A small detachable memory module standing on edge in a foam tray with its row of gold contact fingers catching low light and an empty socket behind it, illustrating why halving the memory on a module does not halve the substrate maker's orders, from korea-stock-guide.com

Three Korean brokerages published on TLB in August and September, all of them building the case on SOCAMM, the detachable memory module Nvidia’s Vera processor uses. None mentions that Nvidia was reported in late July to have halved that module’s capacity from 192 gigabytes to 96 to hold memory under 29 per cent of a 2.1 million dollar system bill of materials. The published numbers reconcile: eight modules per processor, thirty-six processors per rack, 55 terabytes before and 28 after. Module count does not change, and a substrate maker is paid per module. What halves is bits, which belong to Samsung, SK hynix and Micron. The exposure that matters is module count per processor, and nobody has reported a change to that.

SK hynix Did Not Win HBM in 2023. It Won It in 2013.

Card reading Twelve years, five generations, on how SK hynix built its HBM lead and who says it is one, from korea-stock-guide.com

SK hynix approved about 54 trillion won for two new fabs on 7 August 2026, and it targets the clean rooms for December 2028 and June 2029, which means the money does nothing for the HBM4 ramp the company puts in the second half of this year. The lead it is defending is twelve years old: the first HBM in 2013, a through-silicon via part with AMD in 2014, HBM2E in 2020, HBM3 into Nvidia systems from the third quarter of 2022, HBM4 declared complete in September 2025. Every one of those dates comes from the company own newsroom, which is the right source for what shipped and the wrong source for what came first. We mark the two ranking claims we will not print.